The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 1997

Filed:

Aug. 24, 1995
Applicant:
Inventors:

Gary W Jones, Poughkeepsie, NY (US);

Steven M Zimmerman, Pleasant Valley, NY (US);

Susan K Schwartz Jones, Poughkeepsie, NY (US);

Michael J Costa, Poughkeepsie, NY (US);

Jeffrey A Silvernail, Kingston, NY (US);

Assignee:

Fed Corporation, Hopewell Junction, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J / ;
U.S. Cl.
CPC ...
445 50 ;
Abstract

A planarization method for use during manufacture of a microelectronic field emitter device, comprising applying a glass frit slurry including glass particles in a removable base, and subsequently baking to liquify the frit. The invention relates in another aspect to a method of making a microelectronic field emitter device, comprising the steps of: applying a patterned layer of liftoff profile resist over a substrate to define emitter conductor locations; employing the patterned resist layer to form trenches in the substrate at the emitter conductor locations; depositing emitter conductor metal in the trenches and over the patterned resist layer; removing the patterned resist layer; depositing a current limiter layer over the conductors and substrate areas between trenches; depositing a layer of emitter material; pattern masking and etching the layer of emitter material to form emitter structures; depositing gate dielectric; applying a patterned layer of liftoff profile resist over the gate dielectric; evaporating gate metal; and removing the patterned resist layer to define gate electrodes.


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