Memory range detector and translator

Abstract

A split-range address detector and translator for interfacing a system processor with a memory array. The split-range detector generates a select signal for the memory array whenever an input address received from the system processor resides in either of two, non-contiguous, address ranges. The split-range detector includes a first range detector which generates a first range detection signal when the address received from the system processor is within a first, lower, range of addresses, and a second range detector which generates a second range detection signal when the input address is within a second, upper, range of addresses. The output signals are combined together to produce the select signal for the memory array. The address ranges are defined by upper and lower address limits stored within programmable registers. The address translator includes subtraction logic which determines the size of the address gap between the two address ranges from the stored address limits and generates a translated address by subtracting the size of the address gap from the input address. A bus multiplexer responsive to the second range detection signal provides the input address information to the memory array when the input address is within the lower address range and provides the translated address to the memory array when the input address is within the upper range of addresses. Thus, addresses received from the system processor are mapped into a single contiguous address space within the memory array.