Digital phase locked loop circuit

Abstract

A digital PLL circuit has a data sampling circuit for sampling input data in response to N phase clocks in the direction of time. The phase of the clock corresponding to, among the sampled data, the data in which edges are evenly detected is used as a first phase or reference clock. The successive clocks following the first phase clock are used as a second phase clock to an N-th phase clock. The sampled data are rearranged in synchronism with the first phase clock to the N-th phase clock to turn out first phase to N-th phase sampled data. The first phase to the N-th phase sampled data are latched by the first phase clock. The pattern of data received in bursts is identified every period on the basis of the latched first to N-th phase data. Among the latched first to N-th sampled data, the data to be identified are selected. These data are retimed in synchronism with the first phase clock so as to output a phase clock signal.