The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 1997
Filed:
Apr. 19, 1995
Brian Keith Odom, Pflugerville, TX (US);
Bob Mitchell, Austin, TX (US);
National Instruments Corporation, Austin, TX (US);
Abstract
An instrumentation system according to the present invention which automatically demultiplexes multiplexed data received from multiple analog channels. The system includes a plurality N of analog channels that are multiplexed into an A/D converter. The A/D converter in turn supplies the multiplexed or interleaved digital data to an external computer where the data is stored in memory. The external computer includes direct memory access (DMA) demultiplexing logic according to the present invention which automatically reads the multiplexed data and rewrites the multiplexed data into a non-interleaved or demultiplexed format. Once all the multiplexed digital data has been received and stored in the computer system, the demultiplexing logic of the present invention performs DMA transfers to demultiplex or de-interleave the data into N independent buffers or memory spaces which are no longer interleaved. The DMA multiplexing logic performs a transfer for each analog channel to split the data for each analog channel into separate buffers. The DMA demultiplexing logic performs each transfer by incrementing through addresses of the multiplexed data to transfer only the data corresponding to a respective analog channel. The demultiplexing logic increments by the transfer size and an address sequencing value which is the number of analog channels of data in the multiplexed data. In other words, the DMA demultiplexing logic sequences a multiple N times the transfer size, wherein the multiple N is the number of analog channels of interleaved data received by the computer system.