The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 1997

Filed:

Oct. 13, 1995
Applicant:
Inventor:

Hikaru Hida, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257192 ; 257194 ;
Abstract

In an FET structure, an n-type AlGaAs electron supplying layer is provided above a GaAs channel layer, and a low-resistivity n-type GaAs contact layer (the first semiconductor layer) is provided between the source/drain electrode and the electron supplying layer. A high-resistivity AlGaAs layer (the second semiconductor layer) is formed on the sidewalls of the contact layer and the immediately adjacent region between the gate electrode and the contact layer. According to the present invention, since a semiconductor film is used as the thin film formed on the sidewall and the adjacent electron supplying layer instead of a conventional insulating film, and moreover since AlGaAs is substantially lattice matched to GaAs and has a larger band width, parasitic resistance is reduced significantly, and the fluctuation of device performance properties is prevented while still maintaining high breakdown voltage. A semiconductor layer having a conduction type opposite that of the contact layer may also be used in place of the high resistivity AlGaAs layer.


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