Method for fabricating stacked capacitors in a dram cell

Abstract

A one mask/four etch step process to form an curved storage node for an advanced DRAM cell capacitor. A first undoped oxide layer and a second doped oxide layer are formed over associated field effect transistors on the substrate surface. Next, a photoresist pattern having an opening over the node (source) is formed over the second oxide layer. In the first etch step, the second oxide layer is isotropically etched through the opening. The isotropic etch selectively etches the second doped oxide layer thereby forming an arced electrode hole in the second oxide layer. Then in the second etch step, the first oxide layer is anisotropically etched to form the node contact hole. A first conductive layer is formed over resultant surface. A polarization layer is formed covering bottom portions of the first conductive layer but exposing the tops of the first conductive layer. In the third etch step, the exposed tops of the first conductive layer are etched off thereby defining curved bottom storage electrodes. The fourth etch removes the planarization layer and parts of the second oxide. Lastly, a dielectric layer and top plate electrode are formed over the bottom storage electrode. The novel process of this invention produces a capacitor using less masking and etch steps than conventional processes and allows closer spacing between capacitors.