Booth multiplier using data path width adder for efficient carry save

Abstract

A multiplier which uses Booth recoding to multiply large word length operands. A first operand is fully loaded into a shift register. The loading of the second operand is then begun, with the recoding operation beginning after the loading of the minimum number of bits of the second operand required for the first stage of the recoding. The recoded portions of the second operand are used to select what factor of the first operand to use in forming the partial product terms. The partial product terms are added using carry save addition, with the least significant bits being used to form the least significant bits of the final product. The most significant bits of the final product are then formed by adding the partial sum and carry save data from the partial product summations. This summing of the partial sum and carry save data is performed using a data bus width carry look ahead adder instead of the adders used for the partial product accumulation, as is done in typical Booth recoding multipliers.