The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 1997
Filed:
May. 24, 1994
Shigeo Kuboki, Nakaminato, JP;
Norihiko Sugimoto, Katsuta, JP;
Shunji Inada, Hitachi, JP;
Kazuhisa Inada, Hitachi, JP;
Tomoaki Aoki, Ibaraki-ken, JP;
Masahiro Ueno, Hitachi, JP;
Yasushi Nakamura, Hitachiota, JP;
Eiki Kondoh, Hitachi, JP;
Toshihiko Tominaga, Katsuta, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi Engineering Co., Ltd., Hitachi, JP;
Abstract
In a data communication adapter apparatus for a digital data communication connected between a signal transmission path for transmitting both receive data and transmit data, and a host processor unit for producing frame data to output the frame data therefrom, an internal host bus is newly employed in the data communication apparatus irrelevant to the employment of a CPU dedicated bus, and the transmission/reception data generated and interpreted by the host processor is transferred via the internal host bus, a bus interface, and a system data bus between a transmission memory or a reception memory and a buffer memory. Furthermore, a reception memory (host dedicated reception memory) for storing only the reception data to be interpreted by the host processor is separately provided with another reception memory (CPU dedicated reception memory) for storing only the reception data to be interpreted by a CPU, one reception data to be interpreted by the CPU is once transferred from the transmission/reception control unit to the CPU dedicated memory and thereafter read out via the CPU dedicated bus under the control of the CPU, and the other reception data to be interpreted by the host processor is one stored in the host dedicated reception memory and then read out via the internal host bus and bus interface under the control of the host processor.