Computer system including in-circuit emulation mode for debugging system

Abstract

A computer system is provided that includes a microprocessor core having an ICE interrupt line to support an in-circuit emulation mode of the computer system. An interrupt control unit coupled to the ICE interrupt line of the microprocessor core, controls a memory control unit in accordance with assertions of an external 'debug' interrupt signal and an external SMM (system management mode) interrupt signal. During normal operation, the microprocessor core executes code out of a 'normal' memory region of a system memory coupled to the memory control unit. If the debug interrupt signal is asserted while the microprocessor core is operating in normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, causing the microprocessor core to read an ICE vector from the system memory and to thereafter execute ICE code. If the SMM interrupt signal is asserted while the microprocessor core is operating in normal mode, the interrupt control unit again causes assertion of the ICE interrupt signal. The microprocessor core responsively requests the ICE vector and, the interrupt control unit causes the memory control unit to translate the requested address to a second memory location of the system memory at which an SMM vector is stored. The computer system allows an in-circuit emulation mode to be entered while the microprocessor core is executing out of the system management space by asserting the debug interrupt signal.