Integrated circuit memory device having equally spaced apart cell arrays

Abstract

An integrated circuit memory device includes a plurality of memory cell array blocks, each having M columns by N rows and arranged in linear, spaced apart relation in the integrated circuit to produce a row of memory cell array blocks. The row of memory cell array blocks includes first and second outer blocks and at least one inner block therebetween. Each of the outer blocks includes M/2 columns by N rows of dummy cells. Each common area between cell array blocks includes a common input/output circuit block having M/2 columns in each common area, a respective one of which is connected to M/2 columns by N rows of a respective adjacent pair of memory cell array blocks. The integrated circuit also includes input/output lines in each common area and a plurality of input/output circuit blocks, a respective one of which is connected to the input/output lines in a respective adjacent pair of common areas. Preferably, the plurality of memory cell array blocks comprises a plurality of triplets (i.e. integer multiples of three) of memory cell array blocks. A high density memory array structure is thereby provided.