The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 1997
Filed:
Oct. 30, 1995
Richard Raimi, Austin, TX (US);
Carl Pixley, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
Measurement of the test coverage of digital simulation of electronic circuitry is obtained (54). A Composite Circuit Model (60) has two parts: a Target Circuit Model (64) and an Environment Circuit Model (62). The Environment Circuit Model (62) models the behavior of inputs to the Target Circuit (64). The Composite Circuit Model (60) is translated into implicit FSM representations utilizing BDDs. A State Bin Transition Relation is formed which represents allowable transitions among user-specified sets of states or State Bins, and a representation of the reachable State Bins is built (94). A comparison is made (102) between data accumulated over one or more simulations (40) of the Target Circuit (64) and the data contained in the State Bin Transition Relation and the representation of the reachable State Bins. Output (52) is then generated showing which sets of circuit states were and weren't visited and which transitions allowed by the State Bin Transition Relation were and weren't taken during the simulations.