Phase-lock indicator circuit with phase-only detection

Abstract

A phase-lock indicator circuit is disclosed that compares first and second clock signals and indicates when the signals are in-phase. The circuit includes a phase-only detector which is immune to frequency differences. The clock signals are compared by first extracting their leading edges and generating a first pulse signal when the leading edges occur simultaneously. Then, when a consecutive number of first pulse signals has occurred, a second pulse signal is generated, which in turn produces a lock indication signal, indicating that the first clock signal is in-phase with the second clock signal, regardless of whether or not the frequencies of the clock signals are equal. The lock circuit can be used in any PLL circuit regardless of the specific Phase Detector used. The circuit can also be used in any application or circuit where two clocks need to be tracked. In addition, the phase-lock detector includes a loss of input clock feature that indicates if the input clock is lost.