The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 1997

Filed:

Aug. 18, 1995
Applicant:
Inventors:

Yoshiyuki Haraguchi, Hyogo, JP;

Tadato Yamagata, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365226 ; 36518909 ;
Abstract

An SRAM includes a memory cell array, a peripheral circuitry including a bit line load connected to the memory cell array, a multiplexer and the like, and a voltage lowering circuit. The voltage lowering circuit receives a power supply potential Vcc and outputs a potential Vin which is lower. The potential Vin is applied to the peripheral circuitry except the memory cell array, and the power supply potential Vcc is directly applied to the memory cell array. Therefore, operational potential of the memory cell array is made relatively higher with respect to the peripheral circuitry. As a result, a static semiconductor memory device which can operation at low voltage and consumes less power can be provided.


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