Semiconductor memory device having a shortened test time and contol

Abstract

A semiconductor memory device having a shortened test time and a column selection transistor control method therefor. The semiconductor memory device having a plurality of subarray blocks in row and column directions, the subarray blocks storing a plurality of memory cells, including a row decoder for selecting a row of an arbitrary memory cell of the subarray blocks, a column decoder for selecting a column of an arbitrary memory cell of the subarray blocks, a first circuit for inputting/outputting data to/from a specific memory cell selected by the row and column decoders, a second circuit for dividing the inputted/outputted data into a normal mode and a parallel test mode and inputting/outputting the data, and a column redundancy circuit for constituting a decoding of an address in order to replace a column selection line with a spare column selection line by using only an address input used in the parallel test mode and thereby for activating the spare column selection line to test the memory cells in a wafer state.