The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 1997
Filed:
Dec. 20, 1995
Stephen Arthur Smith, Palo Alto, CA (US);
Cirrus Logic, Inc., Fremont, CA (US);
Abstract
A selective low power clocking apparatus and method is used to reduce power consumption by an electronic system or integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits or functional blocks. Each sub-circuit or functional block is configured to operate under control of a clock signal and further includes an apparatus for holding or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, the clock signal to that sub-circuit is disabled. The arbiter circuit continuously monitors the system bus. Upon detecting that the external system needs to transmit or receive signals from the electronic system or integrated circuit, the arbiter re-enables the clock signal to the sub-circuits which are required for the transmission or reception.