The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 1997
Filed:
Nov. 03, 1995
Kanwar J Singh, Matawan, NJ (US);
Pasupathi A Subrahmanyam, Freehold, NJ (US);
Lucent Technologies Inc., Murray Hill, NJ (US);
Abstract
A method for generating a simplified model of a complex binary transistor circuit. A set of Boolean functions are derived for the circuit and these functions are tested to determine if the circuit is stable and binary. All intermediate transient circuit configurations are eliminated so that only direct transitions between stable circuit configurations remain. If the circuit is also combinational, a logic circuit is generated. If the circuit is not combinational but if there is a clock input to the circuit that controls the values of the node (the circuit exhibits synchronous behavior) and all nodes in the circuit are well-defined (either combinational or level-sensitive), a logic circuit is generated. The logic circuit is processed to generate a further simplified logic circuit by merging different types of latches and other logic elements and removing duplicative logic elements.