Phase locked loop circuit with adjustable offset characteristic, method

Abstract

A phase locked loop circuit having a voltage controlled oscillator for generating a clock signal with a frequency determined by a voltage control signal supplied to the voltage controlled oscillator, an AD-conversion circuit for sampling a target signal with a timing determined by the clock signal and for converting sampled values into digital data, a phase locked loop control circuit for generating control data with values representing values of the digital data, and a DA-conversion circuit having an adjustable conversion characteristic for converting the control data into an analog signal and for outputting the analog signal to the voltage controlled oscillator as the voltage control signal. The adjustable conversion characteristic of the DA-conversion circuit is adjusted on the basis of an input signal having predetermined playback characteristics and when the phase locked loop circuit is part of a recording and reproducing apparatus, the input signal is a reproduced signal from a signal recorded on a recording medium.