The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 1997
Filed:
Nov. 27, 1996
Yosuke Mizutani, Hashima, JP;
Seiya Ota, Ama-gun, JP;
Sanyo Electric Co., Ltd., Moriguchi City, JP;
Abstract
A video signal converter comprising a frequency setting circuit, a first clock generator, a second clock generator, an analog-to-digital converter, a line conversion ratio setting circuit, a number of scanning lines converter, a frame memory, a writing controller, a reading controller and a digital-to-analog converter is disclosed. The frequency setting circuit sets a first frequency Fi which satisfies a formula: Fi.ltoreq.(To.times.Fo)/Ti, where Ti is a horizontal scanning period of a first analog video signal, To is a horizontal scanning period of a second analog video signal and Fo is a second frequency. The line conversion ratio setting circuit sets a line conversion ratio R which satisfies an equation: R=m/k, based on a width-to-height ratio 1/m of each pixel of the first digital video data and a width-to-height ratio 1/k of each pixel of second digital video data. The number of scanning lines converter converts any digital video data having a first number of scanning lines to varied digital video data having a second number of scanning lines, the second number of scanning lines being R-times the first number of scanning lines. The writing controller memorizes the first digital video data into the memory in synchronization with the first clock of the first frequency Fi. The reading controller reads the first digital video data from the memory in synchronization with the second clock of the second frequency Fo to generate the second digital video data.