The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 1997

Filed:

Dec. 08, 1994
Applicant:
Inventor:

John Chester Masiewicz, San Jose, CA (US);

Assignee:

Seagate Technology, Inc., Scotts Valley, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
326 82 ; 326 30 ; 375257 ;
Abstract

A mechanism determines at least an approximation of output load coupled to a programmable output buffer, and then programs the buffer to source/sink an amount of output current appropriate to the load to be driven. The mechanism includes a load recognition unit, an optional signal conditioner, and a reconfiguration logic module. In interface-governed applications, the load recognition unit senses an interface bit (AT Attachment interface), or causes the output buffer to act as a master unit that polls the interface connection to determine the number of attached loads (SCSI interface). The recognition unit then outputs a signal that may be conditioned before being input to a reconfiguration logic module that outputs appropriate control signals that program the buffer. Alternatively, the load recognition unit may measure the shunt capacitance associated with the load by using a reference current source and an analog/digital converter. The resultant voltage developed across the shunt capacitance provides a measure of the load impedance, which is used by the reconfiguration logic module to output control signals appropriately configuring the output buffer. Preferably the output buffer includes a plurality of individually-enableable unit buffers. The reconfiguration logic module can enable only such unit buffers whose current handling contributions are necessary to drive the approximated or measured load to be driven.


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