The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 1997
Filed:
Dec. 12, 1995
Tomohiro Kobayashi, Kanagawa-ken, JP;
Yukihiro Fujimoto, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, , JP;
Abstract
A clock signal generating circuit is capable of testing a delay line loop (DLL) circuit by a method wherein, when an LSI circuit operates at a lower speed for a burn-in test, etc., the DLL circuit performs the same operation as when the LSI circuit operates normally at a high speed. This invention includes a selector for selecting either a reference clock signal or a test clock signal having a different phase with respect to the reference clock signal, and a delay line loop system phase-locked loop circuit for giving a delay to an output signal of the selector so as to get rid of a phase difference between the reference clock signal and an internal clock signal that has been propagated through a circuit to be supplied with a clock, and for generating the clock signal to be supplied to the circuit.