The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 1997
Filed:
Mar. 15, 1996
Applicant:
Inventors:
Chao-Ming Koh, Hsinchu, TW;
Bin Liu, Taipei, TW;
Assignee:
Vanguard International Semiconductor Corporation, Hsin-Chu, TW;
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 60 ; 437 47 ; 437 52 ; 437228 ; 437236 ;
Abstract
A method for planarizing a high step-height integrated circuit structure within an integrated circuit. There is first formed upon a semiconductor substrate a high step-height integrated circuit structure. Formed then adjoining the high step-height integrated circuit structure is a patterned Global Planarization Dielectric (GPD) layer. There is then formed upon the exposed surfaces of the semiconductor substrate, the high step-height integrated circuit structure and the patterned Global Planarization Dielectric (GPD) layer a reflowable dielectric layer. Finally, the reflowable dielectric layer is reflowed.