Method and apparatus for identifying and controlling a target peripheral

Abstract

An apparatus and method for controlling devices in a multiple bus system such as a system having two or more ISA type buses. Separate ISA bus controllers may be provided for each ISA bus, linked on a common bus system such as a PCI bus. One ISA controller may be designated as a primary ISA controller whereas other ISA controllers in the system may be designated as secondary ISA controllers. Each ISA controller in the system is provided with IRQ (interrupt request) enable bits to enable different interrupts for the corresponding ISA bus. Each secondary ISA controller outputs a signal IRQSER as a PCI sideband signal to the primary ISA controller to indicate which IRQs have been asserted on the respective ISA buses. The primary controller receives the IRQSER signal as well as the IRQ signals asserted on its own bus and converts these interrupt requests to PCI bus cycles. The primary bus controller may further provide a bit mask indicating which of a number of direct memory access channels are enabled for the primary bus controller. The primary controller receives direct memory access requests from the second bus system and generates a read or write cycle on the first bus system corresponding to outputs requests enabled by the bit mask.