The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 1997

Filed:

Feb. 05, 1996
Applicant:
Inventors:

Najmi Taher Jarwala, Lawrenceville, NJ (US);

Chi Wang Yau, Yardley, PA (US);

Assignee:

Lucent Technologies Inc., Murray Hill, NJ (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B / ;
U.S. Cl.
CPC ...
371 223 ; 371 221 ; 3241581 ;
Abstract

A multi-chip module (10), having n semiconductor chips 14.sub.1 -14.sub.n, each chip having a Boundary-Scan architecture, is rendered Boundary-Scan-compliant both as a circuit board and as a macro-device by the addition of a bypass circuit (36, 36' and 36'). During selected intervals when the module (10) is to be Boundary-Scan-compliant as a macro-device, the bypass circuit operates to bypass the Test Data Input (18) to the Test Data Output (34) of each of n-1 chips. During other than the selected intervals, the bypass circuit allows test information applied to the Test Data Input of each of the chips to be shifted through the chip and to appear at its Test Data Output to facilitate Boundary-Scan compliance of the module as a circuit board.


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