The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 1997
Filed:
Apr. 13, 1995
U.S. Philips Corporation, New York, NY (US);
Abstract
Integrated circuits comprising an EEPROM require a large amount of time for testing, because the write time for a memory cell is very long. Notably the first test after manufacture, with the circuit still present on the wafer, is time consuming. The invention proposes a drastic reduction of the duration of the first test after manufacture by supplying a number of integrated circuits with a voltage in parallel and by providing each integrated circuit with an element whereby several block-wise write cycles for alternately '0' and '1' are executed in substantially autonomously and at the end of the first test step predetermined information is retained. This step is followed by a thermal treatment, after which the integrated circuits are individually contacted and first tested for information retention. For the parallel powering of the number of integrated circuits with an operation voltage during the first test step, supply terminals of the integrated circuits of this number are interconnected across the severing lanes on the wafer and one of the integrated circuits is contacted. When the individual integrated circuits are severed from one another, these conductor tracks are then automatically cut.