Logic synthesis method and logic synthesis apparatus

Abstract

In synthesizing a gate level logic circuit using a computer based on behavioral description of LSI, a logic circuit is first synthesized based on the behavioral description and, then, its power consumption is obtained from the total number of operations. Thereafter, a specific signal propagation path having a larger power consumption is found out from a plurality of signal propagation paths in the logic circuit. A partial logic circuit consisting of logic elements positioned on the specific signal propagation path is optimized in the number of level, thereby creating an optimized partial circuit. Thereafter, obtained is a power consumption of a logic circuit consisting of the optimized partial circuit and the remaining circuit other than the circuit portion optimized. When thus obtained power consumption is small, the partial circuit being not optimized is replaced by the above optimized partial circuit. Accordingly, it becomes possible to reduce overall power consumption while adequately maintaining an area and speed performance of the logic circuit.