The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 1997

Filed:

Aug. 18, 1994
Applicant:
Inventors:

Joseph Robert Kimbrough, Pleasanton, CA (US);

Nicholas John Colella, Livermore, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01H / ; B01D / ;
U.S. Cl.
CPC ...
307126 ; 307131 ; 307125 ; 361 57 ; 250389 ; 340600 ;
Abstract

A 'blink' technique, analogous to a person blinking at a flash of bright light, is provided for mitigating the effects of single event current latchup and prompt pulse destructive radiation on a micro-electronic circuit. The system includes event detection circuitry, power dump logic circuitry, and energy limiting measures with autonomous recovery. The event detection circuitry includes ionizing radiation pulse detection means for detecting a pulse of ionizing radiation and for providing at an output terminal thereof a detection signal indicative of the detection of a pulse of ionizing radiation. The current sensing circuitry is coupled to the power bus for determining an occurrence of excess current through the power bus caused by ionizing radiation or by ion-induced destructive latchup of a semiconductor device. The power dump circuitry includes power dump logic circuitry having a first input terminal connected to the output terminal of the ionizing radiation pulse detection circuitry and having a second input terminal connected to the output terminal of the current sensing circuitry. The power dump logic circuitry provides an output signal to the input terminal of the circuitry for opening the power bus and the circuitry for shorting the power bus to a ground potential to remove power from the power bus. The energy limiting circuitry with autonomous recovery includes circuitry for opening the power bus and circuitry for shorting the power bus to a ground potential. The circuitry for opening the power bus and circuitry for shorting the power bus to a ground potential includes a series FET and a shunt FET. The invention provides for self-contained sensing for latchup, first removal of power to protect latched components, and autonomous recovery to enable transparent operation of other system elements.


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