The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 1997

Filed:

Oct. 19, 1995
Applicant:
Inventor:

Hiroshi Mugiya, Kawasaki, JP;

Assignee:

Fujitsu, Ltd., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
29840 ; 29418 ; 29827 ; 29832 ;
Abstract

A method for manufacturing an apparatus includes the steps of forming a plurality of circuit regions on a single master print circuit board, soldering one or more interconnection leads upon corresponding pad electrodes of the foregoing circuit regions, in a state that the plurality of circuit regions are connected with each other mechanically to form the master print circuit board, and dividing the master print circuit board into individual printed circuit boards each corresponding to one of the circuit regions on the master print circuit board.


Find Patent Forward Citations

Mugiya, Hiroshi. (1997). Fabrication process for circuit substrate having interconnection leads (U.S. Patent No. 5671531). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5671531

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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