Shared memory system and arbitration method and system

Abstract

A shared memory system and an arbitrating method and system. When the processing is distributed over a plurality of CPUs (e.g., CPUA and CPUB) and if it is desired that a shared memory is used to transfer data between the CPUs, a clock CKG indicating the CPUA access timing clock is generated. A gate signal G indicating the access right to the shared memory is generated in synchronism with the clock CKG. When either of the CPUs requests the access to the shared memory, it makes the corresponding chip select signal CSA.sup.- or CSB.sup.- L-level. The access right is always directed to the CPUA and switched to the CPUB in response to the access demand from the CPUB. After one access has completed, the CPUB makes CSB.sup.- H-level. Thus, the access right is switched to the CPUA. After one access has terminated, the CPUA makes CSA.sup.- H-level. If the CPUB requests the access at this time, the access right is switched to the CPUB. If the CPUB does not request the access, the access right is maintained at the CPUA. The CPUA and CPUB are synchronized with each other through a wait signal WAITA.sup.-. When the shared memory is to be accessed, no software is required. The speed of data transfer can be increased and the loads on the CPUs will not influence each other.