The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 1997

Filed:

Oct. 13, 1995
Applicant:
Inventors:

Brian John Machesney, Burlington, VT (US);

Jack Allan Mandelman, Stormville, NY (US);

Edward Joseph Nowak, Essex, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 21 ; 437 41 ; 437 62 ; 437984 ; 148D / ;
Abstract

Structures and methods are presented for forming a body-substrate connector for an SOI FET. The connector is formed substantially co-aligned with the gate conductor on a side of the device that does not interfere with source and drain. The body is thus held close to the substrate potential and the connector provides a path for majority carriers to quickly leave the body. By contacting the body of the SOI MOSFET device in a manner that does not perturb the charge imaged by the gate, parasitic bipolar effects are eliminated while maintaining the desirable attributes of SOI MOSFET devices, such as low substrate bias sensitivity and steep sub-threshold slope. By forming the connector substantially co-aligned with the gate conductor the connection uses little or no surface area.


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