The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 1997

Filed:

Jan. 03, 1995
Applicant:
Inventor:

Shih-Wei Sun, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 21 ; 437 62 ; 437186 ;
Abstract

Interconnects (22 and 32) are formed within an insulating base material of a first substrate. Trenches (54) and portions of an insulating layer (52) are formed within a second substrate (50). The two substrates are bonded by fusion. The second substrate is polished back to form semiconductor islands (81-83) over the first substrate. Active regions of transistors are formed within the islands (81-83). Conductive plugs (131-134) are made between portions of the active regions and interconnects (22, 32, and 141) that underlie or overlie the semiconductor islands (81-83). Embodiments of the present invention allow higher component density, better thickness control for SOI regions, and lower leakage current compared to SOI layers that use LOCOS-type field isolation.


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