The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 1997
Filed:
Jan. 11, 1996
Norio Higashisaka, Itami, JP;
Akira Ohta, Itami, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A variable delay circuit includes a gate chain of first to n-th delay gates (n is an integer larger than 2) connected in series to each other via delay gate wirings having respective wiring lengths, the first delay gate receiving an input signal for delay; first to n-th separator gates to which the outputs of the first to n-th delay gates are input, respectively; first to n-th separator gate wirings having wiring lengths successively shortened from the first to n-th separator gate, first ends respectively connected to the first to n-th separator gates, and second ends connected to an n:1 selector, for selecting one of the outputs of the first to n-th separator gates in according with a select signal, and a select signal generating circuit for controlling the n:1 selector. The variable delay circuit has no loss of resolution due to parasitic capacitance of the delay gate wirings.