The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 1997

Filed:

Jul. 23, 1993
Applicant:
Inventors:

Kazuhiro Kobayashi, Amagasaki, JP;

Hiroyuki Murai, Amagasaki, JP;

Takao Sakamoto, Amagasaki, JP;

Yuichi Masutani, Amagasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438163 ; 438164 ;
Abstract

An Si thin film (2) for a channel is formed on an insulating substrate (1), and then a gate insulating film (3) made principally of SiO.sub.2 is formed thereon. On the gate insulating film (3) is formed a gate electrode (4) composed of a Si thin film doped with impurities. The gate electrode (4) is patterned by isotropic etching using a photoresist (11) as a mask, and the gate insulating film (3) is patterned by anisotropic etching using the photoresist (11) as a mask into a configuration wider than the gate electrode (4) to be removed from source/drain regions position. The Si thin film (2) is ion implanted with impurities to form source/drain regions of an offset structure. A thin film transistor having an offset or LDD structure and capable of reducing an off-state drain current is fabricated without the need for increased number of masks and for an accurate photolithography technique, such as in alignment accuracy between masks.


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