The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 1997

Filed:

Jan. 25, 1996
Applicant:
Inventors:

Kalyan Ganesan, Germantown, MD (US);

Kumar Swaminathan, Gathersberg, MD (US);

Prabhat Gupta, Germantown, MD (US);

P Vijay Kumar, Santa Monica, CA (US);

Assignee:

Hughes Electronics, Los Angeles, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 3701 ; 371 431 ; 375286 ;
Abstract

An improved error control coding scheme is implemented in low bit rate coders in order to improve their performance in the presence of transmission errors typical of the digital cellular channel. The error control coding scheme exploits the nonlinear block codes (NBCs) for purposes of tailoring those codes to a fading channel in order to provide superior error protection to the compressed half rate speech data. For a half rate speech codec assumed to have a frame size of 40 ms, the speech encoder puts out a fixed number of bits per 40 ms. These bits are divided into three distinct classes, referred to as Class 1, Class 2 and Class 3 bits. A subset of the Class 1 bits are further protected by a CRC for error detection purposes. The Class 1 bits and the CRC bits are encoded by a rate 1/2 Nordstrom Robinson code with codeword length of 16. The Class 2 bits are encoded by a punctured version of the Nordstrom Robinson code. It has an effective rate of 8/14 with a codeword length 14. The Class 3 bits are left unprotected. The coded Class 1 plus CRC bits, coded Class 2 bits, and the Class 3 bits are mixed in an interleaving array of size 16.times.17 and interleaved over two slots in a manner that optimally divides each codeword between the two slots. At the receiver the coded Class 1 plus CRC bits, coded Class 2 bits, and Class 3 bits are extracted after de-interleaving.


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