Phase-locked loop timing controller in an integrated circuit memory

Abstract

Interleaved operation of multiple memory banks is improved by including a frequency multiplier and a synchronizing circuit, such as a phase-locked loop, as part of an integrated circuit memory chip. Frequency multiplication supplies additional clock edges for timing different phases of the system clock signal. The synchronizing circuit provide precise control of clock edge timing to exactly align the timing signals in one memory chip with the timing signals in another memory chip despite variability in temperature, process and voltage parameters between the chips.