Integrated seminconductor memory

Abstract

Integrated semiconductor memory having normal memory cells arranged at intersections of word lines and bit lines, decoders for selecting a word line as a function of applicable word line address signals decoders for selecting a bit line as a function of applicable bit line address signals, external reading and evaluator circuits associated with the bit lines of the normal memory cells and connected on an output side thereof with data lines whereat data content is to be output, and redundant memory cells, additionally, by at least one programmable redundant decoder for replacing a defective memory cell, includes external redundant reading and evaluator circuits triggerable by the at least one programmable redundant decoder and associated with the redundant memory cells, the external redundant reading and evaluator circuits being connectible on the input side with the redundant memory cells and on the output side with the data lines, and a redundant control circuit associated with each of the external redundant reading and evaluator circuits, the redundant control circuit being connected to and between the respective associated external redundant reading and evaluator circuit and the data lines and, as a function of a redundant selection signal which is output by the redundant decoder, enabling the data content of a redundant memory cell present at the output of an external redundant reading and evaluator circuit to be transmitted to a selected data line.