The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 1997
Filed:
Apr. 21, 1995
Larry G Jones, Austin, TX (US);
David T Blaauw, Austin, TX (US);
Robert L Maziasz, Austin, TX (US);
Mohan Guruswamy, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A method and apparatus for designing and manufacturing integrated circuits (ICs) involves providing an initial library of IC cells (106) and a behavioral circuit model (100) in order to create a gate schematic netlist (102). The gate schematic netlist (102) is optimized by changing individual transistor sizes, power rail sizes, cell pitch, and the like in a step (103). Once the optimization has occurred, the initial library can no longer be used to place and route the IC. Therefore, a hybrid logic cell library is created from the gate schematic netlist (102) via a step (105). This hybrid library and the above optimizations provides a placed and routed IC via a step (126) in a short design cycle while optimizing performance of the IC.