The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 1997

Filed:

Dec. 22, 1995
Applicant:
Inventor:

Gary Austin Gibbs, San Jose, CA (US);

Assignee:

Cypress Semiconductor Corp., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
326 81 ; 326 33 ; 326 58 ; 326 83 ;
Abstract

A voltage output clamp circuit includes a reference voltage generator, a switched differential operational amplifier, and an output driver circuit. The reference voltage generator has a first input coupled to a first reference voltage and a second input coupled to a second reference voltage. An output of the reference voltage generator is coupled to a first input of the switched differential operational amplifier. The output of the operational amplifier is coupled to an input of the output driver circuit and an output of the output driver circuit is coupled to a second input of the operational amplifier, providing a feedback path. The voltage output clamp circuit may further include a first NAND gate receiving a first logical signal and an output enable signal and providing an output. The output of the first NAND gate may be coupled to an input of a first transistor which is arranged to provide an electrical path between the first reference voltage and the operational amplifier. The voltage output damp may further have a second NAND gate which receives a second logical signal and the output enable signal. An output of the second NAND gate is coupled to the output driver circuit.


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