Method for executing instructions and execution unit instruction

Abstract

A method and apparatus for executing instructions within a processor which completes instructions according to a program order are disclosed. The processor has multiple rename buffers for temporarily storing results of instructions, a number of registers, and an execution unit. The execution unit has a reservation data structure comprising a plurality of entries for storing instructions to be executed by the execution unit and a single operand buffer for storing one or more operands of a single instruction. According to the present invention, an instruction is received at the execution unit. The instruction is then stored within the reservation data structure within the execution unit in association with information specifying a source of an operand of the instruction. Sources of operands of instructions include the rename buffers and the registers. A determination is then made if the instruction is a next instruction to be executed by the execution unit. In response to a determination that the instruction is the next instruction to be executed by the execution unit, the operand of the instruction is loaded from the specified source into the single operand entry. The instruction is then executed within the execution unit utilizing the operand within the single operand entry. By utilizing only a single operand buffer, processor chip area allocated to operand storage within the execution unit is reduced.