The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 1997
Filed:
Mar. 29, 1995
Sachio Hayashi, Saitama-ken, JP;
Tyusei Ogawa, Iwate-ken, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A method for performing compaction of a layout of a semiconductor integrated circuit designed in a hierarchy is described. The compaction of the layout is carried out by repeating a single level compaction process for compacting cell layouts in one of the hierarchical levels from a lowest level to a highest level of the hierarchical levels. The single level compaction process comprises a first replacement step of replacing lower level cell layouts in a current level cell layout with abstract cell layouts having the same profile and the same positions of terminals to be connected to the current level cell layout as the lower level cell layouts have in advance of compaction. The compaction of the current level cell is performed under a constraint that the relocations of the terminals of the current level cell layout after compaction from the original positions before compaction are possible within prescribed ranges. After compaction, the abstract cell layouts is replaced by the lower level cell layouts.