The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 1997
Filed:
Mar. 28, 1996
Judy Lynn Westby, Bloomington, MN (US);
Seagate Technology, Inc., Scotts Valley, CA (US);
Abstract
A 16-bit data block is partitioned into upper 5-bit and 3-bit sub-blocks and lower 5-bit and 3-bit sub-blocks. During a single clock cycle, a first 5B/6B encoder portion encodes the upper 5-bit sub-block to produce an upper 6-bit sub-block, a first 3B/4B encoder portion encodes the upper 3-bit sub-block to produce an upper 4-bit sub-block, a second 5B/6B encoder portion encodes the lower 5-bit sub-block to produce a lower 6-bit sub-block, and a second 3B/4B encoder portion encodes the lower 3-bit sub-block to produce a lower 4-bit sub-block. During the same clock cycle, the running disparities of the upper 6-bit sub-block, the upper 4-bit sub-block and the lower 6-bit sub-block are simultaneously combinationally passed to the first 3B/4B encoder portion, the second 5B/6B encoder portion and the second 3B/4B encoder portion, respectively, to selectively complement the output sub-block to adjust running disparity. During the next clock cycle, the running disparity of the lower 4-bit sub-block is passed to the first 5B/6B encoder for the same purpose.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile