Global planarization using self aligned polishing or spacer technique

Abstract

A method for globally planarizing an integrated circuit device wafer having a plurality of structures disposed on a surface thereof, the structures forming up and down features on the wafer's surface. The method involves depositing a fill layer over the surface of the wafer to cover the structures. Next, an etch mask layer is deposited over the fill layer. After the etch mask layer is fabricated, openings are formed in the etch mask layer to expose areas of the fill layer that are to be subsequently etched. This is accomplished in the first embodiment of the invention by creating self aligned openings in the etch mask layer using CMP if the gaps between the structures are only partially filled. If the gaps between the structures are completely filled, openings in the etch mask layer can be provided by patterning the etch mask layer using lithography and performing an optional spacer deposition and etching step as described in a second embodiment of the invention. In either case, the exposed areas of the fill layer are then etched to provide a second surface having up features that are substantially smaller than the up features originally defined on the surface of the wafer. In the final step of the method, the up features of the second surface are polished to provide a planarized wafer surface.