Semiconductor memory device with an extended data output mode

Abstract

A semiconductor memory with an extended data output mode and the semiconductor memory includes a data output buffer, being always in enable state in the extended mode, for connecting between data output lines and an output terminal; a sense amplifier for sensing and amplifying the data read from a cell and transmitting the amplified data to inner input-output buses; a bus controller, being between the inner input-output buses and the data output lines, for switching connection between the inner input-output buses and data output lines in response to a data path control signal in order to store the data transmitted from the sense amplifier to the inner input-output buses and transmit the stored data to the data output buffer even after occurrence of a column address strobe signal; and a control signal generator for generating the data path control signal which is the combined signal of the signal gained by delaying the front of the column address strobe signal by a first delay time and the signal gained by delaying the rear of the column address strobe signal by a second delay time longer than the first delay time, by which the column address cycle speed can be ensured and the cycle time can be accelerated while ensuring the margin for data transmission sufficiently as well.