The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 1997

Filed:

Mar. 19, 1996
Applicant:
Inventors:

Ken Inoue, Tokyo, JP;

Makoto Sekine, Tokyo, JP;

Hirohito Watanabe, Tokyo, JP;

Ichirou Honma, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
438303 ; 438230 ; 438586 ; 438595 ;
Abstract

The method of fabricating a semiconductor device, includes the steps of (a) forming gate oxides on regions separated by device isolation regions, (b) depositing an amorphous silicon or a polysilicon film, (c) depositing a removable space-forming film over the silicon film, (d) patterning the space-forming film and the silicon film into the same shape to form a gate electrode comprising the thus patterned space-forming film and silicon film, (e) depositing a silicon nitride film, (f) etching the silicon nitride film to form a first sidewall around a sidewall of the gate electrode, (g) depositing a silicon oxide film, (h) etching the silicon oxide film to form a second sidewall around and onto the first sidewall, (i) etching the space-forming film with hydrofluoric anhydride for removal so that the silicon film is exposed and the first sidewall remains unremoved, (j) forming source/drain regions, and (k) selectively depositing a refractory metal or metal silicide film on the silicon film and the source/drain regions. The method makes it easy to cause the first sidewall to have higher height than the amorphous or polysilicon film to thereby form low-resistance gate electrode and diffusion layers, resulting in that the gate electrode is not short-circuited with the diffusion layers.


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