The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 1997
Filed:
Apr. 11, 1994
David Bruce Gingold, Somerville, MA (US);
Kenneth Walter Crouch, Cambridge, MA (US);
Clifford Adam Lasser, Cambridge, MA (US);
Harry Mark Bromley, Andover, MA (US);
Guy Lewis Steele, Jr, Lexington, MA (US);
TM Patents, L.P., Boston, MA (US);
Abstract
An apparatus and method for efficiently mapping elements of an array to processing elements (PEs) of a parallel data computer. Axis lengths and weights are received from a compiler (if invoked at compile time) or an application program (if invoked at run time). A physical grid is generated by expanding the axis lengths so that their product is integrally divisible by 'machine.sub.-- bits' (i.e., log.sub.2 (number of PEs on the data parallel computer)). The physical grid is divided into subgrids of equal size by dividing each expanded axis length into subgrid lengths of equal length. The lengths and numbers of subgrid lengths in each axis are then output to the compiler or the application program. From the subgrid lengths, the compiler or application program can identify a unique location in one of the subgrids given any location of an element in the array. From the number of subgrids in each axis, the compiler or application program can identify a unique memory location on a unique PE given the subgrid and location identified from the subgrid length.