Interrupt modular for receiving bursty high speed network traffic

Abstract

Interrupts are presented to a processor to indicate the arrival of data packets from a high speed network. The rate of packet arrival interrupts is modulated to prevent burdening the processor unnecessarily with repeated interrupts while receiving a burst of data. The interrupt modulator of the present invention ensures that the first packet of a new data burst, or the first packet of a short message, generate an immediate interrupt to the processor, thus avoiding any unnecessary latency in the processor's response. This is done by enabling a packet arrival to generate an interrupt if a specified period of time has elapsed since the previous interrupt. Further, the interrupt modulator ensures that every N'th packet that arrives generates an interrupt--for example, to ensure that the processor performs any memory management functions that may be required. A packet does not generate an interrupt if it arrives soon enough after the previous interrupt and it is not the N'th packet since the pervious interrupt. This lowers the interrupt rate due to the arrival of a burst of data, thus enhancing processor and system performance.