Microprocessor system with hierarchical stack and method of operation

Abstract

A microprocessor including a central processing unit connected to a push-down stack is disclosed herein. The push-down stack includes a first plurality of latches corresponding to a like first plurality of stack elements, and a second plurality of locations of random access memory corresponding to a like second plurality of stack elements. The first and second plurality of stack elements are provided in a single integrated circuit with the microprocessor. The push-down stack further includes a third plurality of memory locations in a system random access memory, with the third plurality of memory locations corresponding to a like third plurality of stack elements. In operation, up to a first plurality of items initially stored in the first plurality of stack elements are transferred therefrom without accessing the second plurality of stack elements. When the first plurality of stack elements are empty, up to a second plurality of items may be transferred thereto from the second plurality of stack elements. Similarly, up to the second plurality of items may be transferred from the second plurality of stack elements without accessing the third plurality of stack elements. In addition, up to a third plurality of items may be transferred from the third plurality of stack elements to the second plurality of stack elements when the second plurality of stack elements become empty.