The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 1997
Filed:
May. 04, 1995
David Wayne Bennett, Louisville, CO (US);
Eric Ford Dellinger, Boulder, CO (US);
Walter A Manaker, Jr, Boulder, CO (US);
Carl M Stern, Boulder, CO (US);
William R Troxel, Longmont, CO (US);
Jay Thomas Young, Louisville, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A device independent, frequency driven layout system and method for field programmable gate arrays ('FPGA') which allow for a circuit designer to specify the desired operating frequencies of clock signals in a given design to the automatic layout system to generate, if possible, a physical FPGA layout which will allow the targeted FPGA device to operate at the specified frequencies. Actual net, path and skew requirements are automatically generated and fed to the place and route tools. The system and method of the present invention evaluates the frequency constraints, determines what delay ranges are acceptable for each electrical connection and targets those ranges throughout the layout.