Multiport register file memory cell configuration for read operation

Abstract

A mulitport register file including a memory cell array having a plurality of addressable memory locations and N bit lines associated with each memory cell in the memory cell array, wherein there are N port inputs to each addressable location in the memory cell array and at most N/2+1 word lines associated with each addressable memory location. A plurality of select and priority circuits having N port inputs and at most N/2+1 outputs, the outputs of a separate select and priority circuit connected to the word lines associated with each of the addressable memory locations to select a single bit line associated with each memory location corresponding to the port input with the highest priority when more than one port input at the same addressable memory location carries an address select signal. Read address comparators and a data transfer unit operate to ensure that the data from the memory cells is also output to sense amplifiers corresponding to the non-selected lower priority port inputs.