The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 1997

Filed:

Aug. 03, 1995
Applicant:
Inventors:

Masahiko Toyonaga, Hyogo, JP;

Michiaki Muraoka, Nara, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364491 ; 364489 ;
Abstract

An automatic layout of a data-path circuit, whose performance and area are optimized, requires to input a data-path circuit, produce an external terminal directive branch having a start point placed on an input terminal group of the data-path circuit and an end point placed on an output terminal group of the same, and produce in-circuit directive branches corresponding to respective connecting lines between two circuit elements in the data-path circuit, each in-circuit directive branch having a start point placed on one circuit element supplying a signal to a related connecting line and an end point placed on the other circuit element receiving the signal from the same connecting line. Subsequently, a group circuit is produced based on the relationship between the in-circuit directive branches and the circuit elements, the group circuit comprising a plurality of circuit elements performing a series of logic processing per 1-bit signal. A layout evaluation is then produced so as to comprise an evaluation satisfying a requirement that a direction of the external terminal directive branch is met with directions of the in-circuit directive branches. Thereafter, the layout of circuit elements is optimized based on the layout evaluation and the resultant layout is outputted.


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Toyonaga, Masahiko. (1997). Method and apparatus for automatically arranging circuit elements in (U.S. Patent No. 5657243). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5657243

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