Method and apparatus for reading ahead display data into a display fifo

Abstract

A graphics controller that uses two MREQ priority levels (low and high) to retrieve display data from a frame buffer into a CRT FIFO. The graphics controller sends the high priority MREQ signal to a host controller if the data level in the CRT FIFO is below a low level water mark. The graphics controller sends the low priority MREQ signal if the data level in the CRT FIFO is between a high level water mark and a low level water mark, and if a system memory bus is idle. The host controller grants access of the system memory bus to the graphics controller with a higher priority (i.e. above that of other devices such as CPU and I/O devices) in response to the high priority MREQ signal, and with a lower priority in response to the low priority MREQ signal. Upon being granted access to the system memory bus, the graphics controller retrieves display data from the frame buffer. By employing the low priority MREQ signal, the system memory bus is more efficiently utilized and the frequency of high priority MREQ signals is minimized which leads to an overall increase in the throughput performance of the information processing system.